1. Field of the Invention
The present invention relates to a method and an apparatus for controlling shared memory and a method of accessing the shared memory, and more particularly, to a method and an apparatus for sharing a memory to store data interchanged between a processing unit for processing an application program and a user program unit for executing a user program based on the application program of the processing unit.
2. Description of the Related Art
A general-purpose processor (GPP) reference board is a board designed to allow system developers to refer to the GPP.
In order to realize desired systems, the system developers may design a field-programmable gate array (FPGA) daughter board, mount the FPGA daughter board on the GPP reference board, and embody related software. Also, in order to embody and verify developed communication protocols and application specific integrated circuits (ASICs), there is a growing tendency for the system developers to realize FPGA device drivers in accordance with FPGA logic designs and GPP operating systems.
Accordingly, a communication protocol may be required to reciprocally transmit and receive control signals and data between the GPP and an FPGA. In a conventional method of interchanging messages, a GPP and an FPGA may transmit and receive messages through a random access memory (RAM) included in the FPGA. In another method, a GPP and a dual-port RAM (DPRAM) may be connected to each other by a system bus, and the DPRAM and an FPGA may be connected to each other by a local bus. Thus, the DPRAM may be designated as a critical section so that messages may be interchanged between the GPP and the FPGA while ensuring data integrity. Here, the critical section refers to a section of source code that accesses shared resources in an exclusive fashion.
Meanwhile, since a GPP reference board is designed to allow the expansion of a system bus, an FPGA, a complex programmable logic device (CPLD), a buffer configured to relay bidirectional transmission and reception of data, and a DPRAM may be mounted on a daughter board or other devices so that the GPP and the FPGA may interchange a large amount of messages through the DPRAM having an abundant memory space.